1. Field of the Invention
The present invention relates to redundancy circuits and methods for built-in self repair of a semiconductor memory device with failed memory elements.
2. Description of the Related Art
Semiconductor memory devices are generally organized in a two-dimensional array, wherein the memory elements are located at the intersection of rows, or "word lines," and columns, or "bit lines," of the array. To access a given memory element, it is necessary to select the word line and the bit line at the intersection of which the memory element is located. For this purpose, memory addresses are divided into row and column address signals, which are decoded independently.
In the manufacture of semiconductor memories, defects are frequently encountered that affect a limited number of memory elements in the memory array. In order to prevent rejection of an entire chip due to the presence of a comparatively small number of defective memory elements, and thereby increase manufacturing process yield, the typical manufacturing technique provides for a certain number of redundant memory elements.
Redundant memory elements have been used as replacements for those elements that, during testing of the memory device, prove defective. Redundancy circuitry typically includes laser programmable fuses or other non-volatile memory elements suitable to store those address configurations corresponding to the defective memory elements. Laser programmable fuses have several disadvantages including requiring significant testing and laser programming manufacturing infrastructure. Furthermore, laser programmable fuses are large compared to feature sizes achievable with typical modem process techniques and, as a result, create layout problems when required on pitch. Laser programmable fuses must be programmed prior to packaging and therefore cannot be used to replace defects that develop during burn-in.
For at least some of these reasons, other non-volatile memory elements such as electrically programmable fuses or floating-gate MOSFETs have been used to store address configurations corresponding to defective memory elements. For example, U.S. Pat. No. 5,313,424 to Adams et al., entitled "Module Level Electronic Redundancy" and issued May 17, 1994, discloses an array built-in self-test (ABIST) system in which electrically programmable fuses can be programmed after packaging to encode faulty cell addresses.
Another built-in self-test (BIST) and built-in self-repair (BISR) design is disclosed by T. Chen et al., "A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories," in Proc. IEEE ITC 1992, pp. 623-631. Self-testing is performed by a 13N algorithm. During self-testing, an address generated by an address generator is supplied to an address decoder which in turn addresses into a memory array. Test patterns are generated by a data generator and data are written to and read from the memory array under control of a state machine. A comparator compares data read from the array with data generated by the data generator and, if a fault is detected, latches the faulty address into a fault signature block. During memory access operations, the faulty addresses stored in the fault signature block are used to divert (or redirect) an access to a faulty address to a non-faulty redundant address. A memory access address is compared to contents of the fault signature block and, if a match occurs, the access is redirected to a redundant address. Redirection is provided by an address correction block which supplies a corrected address to the address decoder which in turn addresses into a memory array. Chen's approach provides a flexible address redirection based method for a self-repairing memory. Unfortunately, Chen's fault signature block places address comparison with contents of the fault signature block on the critical path to the address decoders.
U.S. Pat. No. 5,577,050 to Bair et al., entitled "Method and Apparatus for Configurable Build-In Self-Repairing of ASIC Memories Design, filed Dec. 28, 1994 and issued Nov. 19, 1996 discloses a similar BISR design, wherein faulty row addresses are stored in a fault signature block and corresponding entries in an address correction block are used as substitute address for supply to a memory array. Like Chen's design, Bair's design places address comparison with contents of the fault signature block on the critical path to array addressing. Accesses to both normal and redundant addresses are necessarily delayed by (1) lookup into the substitute address table formed by fault signature and address correction blocks and (2) decode of the supplied or substituted address. Such delays can adversely affect memory access cycle times.